Principal Engineer, eFPGA Place and Route

Principal Engineer, eFPGA Place and Route page is loaded## Principal Engineer, eFPGA Place and Routelocations: US, CA, San Jose, Rio Roblestime type: Full timeposted on: Posted Todayjob requisition id: R256124**About Analog Devices**Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at and on and .# **Principal Engineer, eFPGA Place and Route****The Group:**The charter of ADI’s eFPGA team is to co-develop an industry leading heterogenous processing system deploying embedded Field Programmable Gate Arrays (FPGAs) for high-speed, real-time hardware adaptation. An on-going requirement for this capability is the development and support of FPGA backend toolset including timing-driven implementation suite (optimization, place and route, bitstream), reporting (area, timing, power) and debug capabilities. This software suite will be a key part of a larger heterogenous co-processing development environment allowing the ability to design leading-edge products in a variety of applications and markets.**The Position:**The group is seeking an experienced Principal Engineer to lead and contribute to the development of next generation eFPGA backend tools. This person will manage a small team of highly motivated individuals to guide the realization of an industry-leading eFPGA toolset as well as participate to the overall engineering effort.**Responsibilities*** Manage and motivate a small team of software development engineers to drive all aspects of eFPGA place and route: + Database management + Netlist import & resource estimation + Floorplan import or automatically floorplan creation + Wire-length & timing-aware placement + Congestion & timing-aware optimization + Congestion & timing-aware routing + Static timing analysis with support for common SDC syntax + Bitstream generation* Work closely with synthesis tools providers (Synopsys & Yosys) to efficiently target our devices, especially our DSP and BRAM cells* Work closely with software Q&A and applications teams to understand and fulfill software requirements and priorities + File and track software issues and tasks to closure in JIRA + Document results of assigned tasks and review the results with the team* Contribute towards verification strategy and methodology improvement + Support verification of bitstream simulation & silicon debug + Support and establish formal verification targeting automotive requirements*For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.**Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.**EEO is the Law: .*Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $170,775 to $256,163.* Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.* This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.* This position includes medical, vision and dental coverage, 401k, paid vacation, **holidays, and sick time**, and other benefits. #J-18808-Ljbffr