Design Verification Engineer (Santa Clara)
Job Description: Design verification engineer:
Location: Santa Clara, CA \ Austin, TX \Boston, MA - Onsite
PREFERRED EXPERIENCE:
8+ years experience in Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the likes.
Looking for coherency knowledge (if possible) and complex topics in PCIe (like ordering etc).
Strong understanding of assertion(SVA/OVL) and coverage-based methodologies.
Exposure to RTL design, software development, formal verification, or other related domains.
Good understanding of computer organization/architecture.
Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
KEY RESPONSIBLITIES:
Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design.
Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design.
Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
Collaborate with architects, hardware engineers, and multiple IP development groups.
Drive formal verification for the block and write formal properties and assertions to verify the design
Responsible for verification quality metrics like pass rates, code coverage and functional coverage
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in computer engineering/Electrical Engineering preferred.
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