DDR Mixed-Signal Circuit Design Engineer
DDR Mixed-Signal Circuit Design Engineer
San Francisco Bay Area, California, United States Hardware
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? We have an opportunity for a detailed and extraordinarily hardworking PHY Analog/Mixed-Signal Circuit Designer. As a member of our multifaceted group, you will have the unique and great opportunity to shape upcoming products that will delight and inspire millions of Apple’s customers every day!In this role, we are the center of a PHY design effort collaborating with Platform Architecture, Logic Designers, SIPI, Layout, DV and Timing Teams, with a critical impact on delivering best in class PHY designs. You will be required to do transistor level Analog/Mixed-Signal Circuit Designs, working with Layout Teams on the physical implementation of industry leading PHY designs. The ideal candidate will have significant experience in Analog/Mixed-Signal Circuit Design.
Description
As an Analog/Mixed-Signal Circuit Design Engineer, you will be involved with all phases of high-performance PHY designs from architectural concept to delivery of our final GDS.
Responsibilities
- Created detailed specifications for analog / mixed signal IP
- Design analog / mixed signal IP from the high level concept to the transistor level, delivering the final GDS and required collaterals
- Supervise Layout Designers as they create the IP GDS
- Run pre silicon verification flows to ensure the design’s robustness
- Characterize the silicon and debug as needed
Minimum Qualifications
- BS and a minimum of 10 years relevant industry experience
Preferred Qualifications
- Proven understanding of all aspects of Analog/Mixed Signal Circuit Design of PHYs. TX, RX, Delay Locked Loops, Phase Interpolators, Delay Lines, Duty Cycle Correctors, reference generators, etc.
- Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able to collaborate with logic design team.
- Solid understanding of Circuit Verification tools (Simulators, Extraction, EMIR, Noise, SigEM, etc.).
- Generate block/chip level specifications.
- Perform block level verification to close the design by meeting performance, power and area specifications.
- Participate in establishing Design Methodologies to ensure accurate, by construction designs.
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Apple accepts applications to this posting on an ongoing basis.
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