Formal Verification Engineer - Applying LLMs for Chip Design (San Jose)

Job Description

About Us

Chips are at the center of today's tech-driven world. But how we design them has not changed in decades, while their complexity and specialization have skyrocketed due to increasing performance demands from applications like AI. We want to change that.

Our team is small, technical, and fast-moving. Weve built and shipped at the intersection of AI, EDA, and systems software, with deep roots at companies like Qualcomm, Nvidia, Google, Meta, and the Allen Institute for AI. Were backed by top investors including Khosla Ventures, Cerberus, and Clear Ventures, and already deployed with 10+ innovative customersfrom Fortune 100s to cutting-edge AI silicon startups.

About This Role

We are looking for an experienced Formal Verification Engineer to join our dynamic team. The ideal candidate has experience with all aspects of Formal Verification SVA, Property Verification, Formal Methods/Abstractions, Methodology, and scripting. You will work on developing Chipstacks revolutionary Formal Verification Agent , directly impacting the tool quality and features.

You will collaborate with highly experienced chip designers, ML scientists, and top-tier infrastructure and software engineers. You will leverage your expertise in Formal Verification to build next-generation AI-enabled Verification tools.

Key Responsibilities

• Collaborate with ML and software teams to develop advanced, AI-driven chip design and Formal Verification solutions.
• Work closely with ML leads to understand and implement cutting-edge technologies in chip design.
• Engage directly with customer projects, applying your expertise to develop practical and innovative solutions.
• Contribute to integrating LLM technologies into the chip design process to enhance efficiency and performance.
• Stay updated with advancements in chip design and AI/ML technologies to continually improve methodologies and solutions.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
• Strong experience in Formal Verification, including implementing complex testbenches using Formal Methods.
• Proficient in SVA and SystemVerilog; experience with tools like JasperGold, VCFormal, Verdi.
• Solid programming skills (Python, C/C++, Verilog, SystemVerilog).
• Interest or experience in AI/ML, especially in LLMs, is highly desirable.
• Strong problem-solving skills and proactive learning attitude.
• Excellent communication skills and team-oriented mindset.
• Self-motivated, driven, and comfortable tackling challenging, unexplored areas.

Why Join Us?

As a Silicon Valley-funded startup, this is a unique opportunity:

• Personal impact Build from the ground up and define a new industry-standard product.
• Learning opportunities Access to talks by AI researchers, community knowledge sharing, and collaboration with diverse experts.
• Founding title Be one of our first hires, with lasting recognition.
• Early-stage equity Share in the company's potential success.
• Benefits Health insurance, catered lunches, and more, despite our early-stage status.