Design Verification Engineer, Principal

Position Title: Design Verification Engineer, Principal (Confidential Client)
Location: Santa Clara, CA | Onsite
Employment Type: Permanent

Compensation

• Salary: $158,600 - $317,800/yr
• Variable Compensation: Base, bonus, RSUs, Refresher RSUs

Position Summary

As part of the Design Verification Team at Our Client, you will verify all of the circuitry that goes inside chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets customers' specifications whether they're a major telecom organization or automotive company, etc. As a leading member of the Network Switching team you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development. Your role may also include project management and leading a team of verification engineers on a project level.

Primary Functions

• Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete
• Developing tests and tuning the environment to achieve coverage goals
• Debugging failures and working with designers to resolve issues
• Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs
• Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment
• Unit and regression testing of software tools

Must-Haves

• BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience)
• Proven track records of leading Design Verification implementation activity. Tape-out of complex SOC under tight schedule
• In depth understanding and experience with System Verilog, UVM
• In depth experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment
• Experience with scripting language such as Python or Perl and EDA Verification tools
• Experience with Object-Oriented Design and implementation
• Good understanding of Linux O.S.
• Good programming skills desired, especially C++ and ARM assembly
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision
• Requires the ability to accept and work with differing opinions
• Cannot be a close-minded developer
• Must be able to learn on the fly and work in a fast-paced environment

Preferred Qualifications

• Understanding of networking protocols