Staff Analog IC Layout Engineer

Elevate Semiconductor is at the forefront of shaping the future of semiconductor technology, driving innovation to enable the next generation of testing. We deliver comprehensive solutions that streamline semiconductor testing, empowering faster time-to-market and enhanced capabilities. Our diverse product portfolio includes standard, semi-custom, and custom SKUs, all engineered for longevity and compatibility across evolving technological advancements. By focusing on low-power, high-density designs, we aim to lower the cost of testing while exceeding expectations on every project.

Join us in advancing the cutting edge of semiconductor innovation!

The Position

We are seeking a highly skilled Staff Analog Layout Engineer to join our team in developing state-of-the-art integrated circuits (ICs). In this role, you will handle the physical layout and verification of highly complex, high-voltage, and mixed-signal solutions using advanced process technologies, ranging from 65nm CMOS to 100+V BCD. You will collaborate with a cross-functional team to optimize silicon design, leveraging mentorship and support from senior engineers to deliver innovative and cost-effective solutions.

Must be able to work onsite in San Diego,CA.

Responsibilities

• Performing physical layout of analog and mixed-signal integrated circuits at the block and chip level
• Conducting floorplanning and placement of circuit components to optimize area, performance, and power
• Verifying layouts using industry-standard tools for LVS (Layout vs. Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules
• Collaborating closely with design engineers to understand circuit specifications and ensure layout accuracy
• Working with cross-functional teams, including digital design and packaging, to optimize overall chip performance
• Troubleshooting and resolving issues related to layout verification and manufacturing

Requirements

• Bachelor’s degree in Electrical Engineering or a related field
• Minimum of 8 years of professional experience in analog and mixed-signal IC layout design
• Strong knowledge of analog CMOS circuits and device physics fundamentals
• Solid understanding of the IC design, qualification, and manufacturing lifecycle
• Hands-on experience with industry-standard EDA tools for analog and mixed-signal design (e.g., Cadence, Mentor Graphics, Tanner)
• Proficiency in performing LVS and DRC verification using Cadence or Mentor tools

Preferences

• Layout experience with STI High voltage (100V+) BCD and LDMOS processes
• Layout experience with mixed voltage (multiple supply rails, 6 or more) domains
• Layout experience with high speed multi Gbps circuits.
• Layout experience in ultra-high accuracy and precision circuits.
• Layout experience with high resolution data converters.
• Layout experience with BiCMOS process technology.
• Programming and scripting ability a strong plus, particularly in SKILL and Calibre scripts

Why Join Us?

At Elevate Semiconductor, you’ll be part of a dynamic team working on innovative technologies that shape the future of the semiconductor industry. We offer competitive compensation, comprehensive benefits, and opportunities for professional growth in a collaborative environment.

Apply Today!

If you are passionate about digital design and eager to contribute to groundbreaking semiconductor solutions, we want to hear from you!

Benefits

• 100% Employer Paid Health Insurance (Medical, Dental, Vision)
• Unlimited Paid Time Off
• Performance Bonuses
• Free Lunch Catered in by Local Restaurants
• Private Equity Options
• Retirement Plans
• Sabbatical Program
• Tuition Reimbursement
• Volunteer Days
• Relocation Assistance
• Conference Attendance Support
• Biweekly Phone Stipend
• Employee Assistance Program

The salary range for this role is $120,000-$180,000.00.

Please note: While a salary range is provided, the final compensation will depend on your experience, skill set, and how well you're able to highlight your background throughout the interview process.