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DFT Engineer

Broadcom
San Jose, CA
DFT Engineer Location San Jose, CA : Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. 2. If you already have a Candidate Account, please Sign-In before you apply. : DFT Engineer Broadcom's ASIC Product Division is seeking candidates for a DFT Lead position at our San Jose, California Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production. The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)'s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement. This job opening has a particular emphasis on Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers. It is expected that you can code using TCL, PERL, RUBY, PYTHON, C++ or similar. Responsibilities:
  • Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
  • Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
  • Working closely with STA and DI Engineers design closure for test
  • Generating, Verifying & Debugging Test vectors before tape release.
  • Validating & Debugging Test vectors on ATE during the silicon bring up phase
  • Driving silicon failure analysis, diagnostics & yield improvement efforts
  • Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
  • Working closely with I/P DFT engineers & other stakeholders
  • Debugging customer returned parts on the ATE
  • Innovating newer DFT solutions to solve testability problems in 7nm & beyond
  • Automating DFT & Test Vector Generation flows
    • Skills/Experience:
    • Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
    • Scan Insertion and scan compression background (DFT Compiler, Siemens TestKompress, etc.)
    • Well-versed in ATPG vector generation, simulation, debug.
    • Experience in Verilog coding, testbench generation & simulation
    • Memory BIST insertion and verification experience (SRAM, CAM, eDRAM)
    • The ability to work in a multi-disciplined, cross-department environment Solid knowledge in analog and digital circuit design, and device physics fundamentals Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
    • Excellent problem solving, debug , root cause analysis and communication skills
    • Experience working on ATE is highly desired
    Education & Experience:
    • Bachelors in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience.
    Additional : Compensation and Benefits The annual base salary range for this position is $126,000 - $210,000. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Posted 2025-09-10

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