Senior Principal Analog Power Management Integrated Circuit (PMIC) Design Engineer (Technical Lead)

About Us

Red Cell Partners is an incubation firm building and investing in rapidly scalable technology-led companies that are bringing revolutionary advancements to market in three distinct practice areas: healthcare, cyber, and national security. United by a shared sense of duty and deep belief in the power of innovation, Red Cell is developing powerful tools and solutions to address our Nation’s most pressing problems.

About Claros

Claros innovates at the intersection of power and compute. We build advanced semiconductor power management solutions that improve AI compute capacity, efficiency and reliability. Claros is an early-stage startup company located in Torrance, CA. If you are looking for challenging work and a strong technical environment with the collaborative & supportive culture, then Claros Tech is the company for you. We offer industry the best competitive pay & benefits and early-stage stock options.

Location: Minimum of 3 days a week in the office in Torrance, CA.

About the Team:

We are open-minded, fast paced, problem solvers that value open dialogue and candor. Our passion is to challenge the status-quo and we embrace transformational thinking. Our response is never “no, but….” instead “yes, if….”. We are mindful of our personal and organizational blinders and try to build an environment where our team members are At Their Best.

About The Role

Claros Inc. is seeking to hire an exceptional Senior Principal Analog Power Management Integrated Circuit (PMIC) Design Engineer (Technical Lead) to join our ASIC team in Torrance, CA. Candidate must be self-motivated individual to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering PMICs (Low-dropout (LDO) linear voltage regulators, Switching regulators, DC-DC Buck Converters), ADC/DAC, PLL, Gate Drivers, and PMIC chip integration). As a Senior level tech lead, you'll play a crucial role in design and development of Power management ICs from concepts into release to production, collaborating closely with other circuit designers, and leveraging sophisticated tools.

This role will report to the VP of Engineering.

What You Will Do

In this role, you will be responsible for the design and development of high-performance analog circuits for PMICs used in a range of applications.

• Collaborate with other engineers to define and implement design methodologies and best practices for PMIC design and related areas.


• Plan and lead a group of designers in implementation of commercial product.


• Work with multi-disciplinary teams including R&D, systems, testing to implement new ideas and in writing the specifications, design, characterization, verification and documentation.


• Summarize and interpret results of highly complex performance checks and review it with team.


• Use problem solving skills, experience, and supervise the layout circuit designers. Guide them with floor planning and in resolving DRC/LVS errors.


• Behavior and transistor level circuit design, simulation and verification of power management blocks including LDO, Switch Mode Power Supplies (buck, boost), voltage reference and other analog circuits meeting power, performance and area specifications.


• Work closely with PCB layout engineers to ensure performance and quality of the designs.


• Work with team on best packaging approach for design and test.


• Datasheet drafting and reviews .


• Work with product managers to develop the next generation of products .

What You Bring

• Bachelor’s degree in electrical engineering with 8+ years of overall experience in analog/mixed signal IC Design.


• Knowledge of semiconductor manufacturing processes and their impact on analog circuit design. Experience is designing circuits in High voltage (BCD) technology processes and FinFET technology (like 12nm and below) is preferred.


• Strong background in Power Management devices and circuit design principles, Buck Converters Architecture & Design, Mixed Signal Design, Gate Drivers, PLL & Clock Chip Design.


• Must have released at least one full IC design from Concept to release to production.


• Good knowledge in device physics and device reliability analysis.


• Proficiency in using Cadence IC Design Tools.


• Familiarity with industry standard interface protocols such as SPI, I2C, PMBus/SMBus.


• Ability to document design techniques, test and verification methodology.


• Conduct design reviews, analyze and debug circuits, and perform system-level testing to validate performance and ensure compliance with specifications.


• Full chip integration and Top-Level Simulations.


• Strong analytical and problem-solving skills, with the ability to debug complex issues.


• Excellent communication and collaboration skills to work effectively in a team environment.


• Ability to effectively prioritize and execute tasks in a high-pressure environment.

What Is Helpful

• Master’s degree in electrical engineering with 5+ years of overall experience in analog/mixed signal IC Design.


• Knowledge in writing Verilog/VHDL modeling.


• Experience with layout design, layout review, and layout versus schematic (LVS) verification.


• Knowledge in Python/Perl script development and MATLAB simulations are a plus.

What We Offer

• Career track opportunity with potential for rapid advancement with strong performance as the firm grows.


• 100% employer paid, comprehensive health care including medical, dental, and vision for you and your family.


• Paid maternity and paternity for 14 weeks at employees' normal pay.


• Unlimited PTO, with management approval.


• Opportunities for professional development and continued learning.


• Optional 401K, FSA, and equity incentives available.

Salary Range : $180,000-$220,000. This represents the typical salary range for this position based on experience, skills, and other factors.

We’re an Equal Opportunity Employer: You’ll receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, protected veteran status, or on the basis of disability.