ASIC Digital Design, Sr Staff Engineer-10280 (Sunnyvale)

The work location for this position is Ottawa. However, t he hiring manger may be open to consider candidates willing to work out of Toronto locations.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned ASIC Digital Design Engineer with a passion for innovation and a proven track record of delivering complex designs in high-speed, leading-edge technology environments. With years of experience in RTL development, you thrive at the intersection of digital, analog, and mixed signal design. Your deep expertise in SystemVerilog and Verilog, coupled with your ability to model and interface with analog and mixed signal circuits, sets you apart as a technical leader. You are adept at translating architecture and industry-standard specifications into robust, high-performance RTL solutions, ensuring seamless integration into advanced SoC environments.

Your experience spans the entire ASIC and IP development flow, including DFT/DFM, physically aware synthesis, and debugging at both the block and system level. Exposure to DDR and HBM DRAM technologies is a strong asset.

What Youll Be Doing:

• Architecting, developing, and delivering RTL designs for High Bandwidth Memory PHY IP, leveraging SystemVerilog and Verilog.
• Collaborating closely with analog and mixed signal design teams to ensure seamless integration and optimal performance.
• Translating architecture and industry-standard specifications into clear, implementable RTL and technical documentation.
• Automating design flows and verification processes using scripting languages to enhance productivity and streamline development.
• Debugging complex hardware issues at both the RTL and system levels, including physically aware synthesis and timing closure.
• Participating in and guiding the full ASIC and IP development lifecycle, including DFT/DFM flows and design reviews.
• Mentoring junior engineers and fostering knowledge-sharing across global teams.

What Youll Need:

• 8+ years of experience in ASIC RTL design, including interfacing with mixed signal designs.
• Expert proficiency in SystemVerilog and Verilog for high-speed digital design and modeling.
• Strong background in high-speed circuit design, timing closure, and physically aware synthesis.
• Proficiency in scripting languages (e.g., Python, Perl, TCL) for automating design and verification tasks.
• Comprehensive understanding of the ASIC and IP development flow, including DFT/DFM.
• Experience in debugging complex hardware issues and writing clear specification documents.
• Familiarity with DDR and HBM DRAM technologies is highly desirable.

Who You Are:

• Analytical and detail-oriented, with a proactive approach to problem-solving.
• Effective communicator, able to articulate complex technical concepts to diverse audiences.
• Collaborative team player who thrives in a global, multicultural environment.
• Adaptable and resilient, embracing new challenges and continuous learning.
• Mentor and leader, committed to supporting the development of others.
• Passionate about innovation and delivering high-quality solutions

The Impact You Will Have:

• Enable Synopsys to deliver world-class High Bandwidth Memory PHY IP, accelerating customers time-to-market for advanced SoC products.
• Drive innovation at the boundary of digital, analog, and mixed signal design, pushing the limits of memory performance and integration.
• Enhance the reliability and quality of delivered IP through rigorous verification and debugging.
• Contribute to the worlds broadest portfolio of silicon IP, supporting diverse applications from AI and cloud to 5G and IoT.
• Empower global teams by sharing expertise and best practices, cultivating a culture of technical excellence and collaboration.
• Reduce design risk and optimize power, performance, and area for customers next-generation chips.

The Team Youll Be A Part Of:

Youll join the High Bandwidth Memory RTL team, a group of experienced engineers dedicated to designing cutting-edge PHY IP at the interface of digital, analog, and mixed signal technology. This diverse, global team values collaboration, technical rigor, and continuous improvement. Together, youll drive the integration of advanced memory capabilities into next-generation SoCs, supporting Synopsys leadership in silicon IP.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#LI-NK4