Digital Design Engineer
Role: Digital Design Engineer
Location: Mountain View, CA
Duration: 1 Year
Must-Have Skills:
- 5+ years FPGA design (Xilinx: Versal, UltraScale+, 7-series)
- RTL coding in Verilog/SystemVerilog, synthesis, SoC integration
- Digital design Architecture experience
- Scripting: Python, TCL, Shell
Nice to Have:
- Experience with PCIe, USB, MIPI, SPI, I2C, C/C++
- RTL-to-GDS flow on advanced nodes (e.g., TSMC N7)
- Firmware development and FPGA bring-up
Education: B.S. in EE/CE/CS (M.S. preferred)
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