DFT (Design for Test) Engineer.
DFT (Design for Test) Engineer.
Location: Santa Clara, CA
Key Skills & Experience
- Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite.
- Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing.
- Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improvement.
- Experience with MBIST (Memory Built-In Self-Test), including memory test architecture, implementation, and diagnostics.
- Good knowledge of IO Test methodologies for interface and pin-level validation.
- Strong understanding of Clock DFT and clock verification concepts.
- Solid foundation in Digital Design and RTL (Verilog/SystemVerilog).
- Experience with industry-standard DFT/ATPG EDA tools.
- Experience in verification of DFT features, including Boundary Scan (JTAG), IJTAG, MBIST, High-Speed Scan Testing, and other DFT methodologies.
- Excellent analytical, debugging, and problem-solving skills.
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